And if TSMC pushes them from 40nm to 28nm the M0+ cores and SRAM should scale to even higher clock rates without drawing too much power. While the RP2040 is "only" specified at up to 133MHz it has been reported stable at over twice that. From the scattered reports at least the AHB-lite bus matrix, SRAM and CPU cores are stable up to ~400MHz which more than compensates for the lower per clock throughput on anything but floating point heavy code.
The RP2040 isn't perfect, but it's a good starting point for more capable/specialised chips e.g. variants with high speed USB, 100Mb/s MAC, just scaled up (four M0+ cores, 8way interleaved memory banks, additional PIO and DMA engines, dual QSPI).
Just upgrading to a good dual QSPI peripheral would make the chip more versatile allowing users to choose between different external memory configuration like SPI flash and PSRAM or higher combined flash read bandwidth.
The RP2040 isn't perfect, but it's a good starting point for more capable/specialised chips e.g. variants with high speed USB, 100Mb/s MAC, just scaled up (four M0+ cores, 8way interleaved memory banks, additional PIO and DMA engines, dual QSPI).
Just upgrading to a good dual QSPI peripheral would make the chip more versatile allowing users to choose between different external memory configuration like SPI flash and PSRAM or higher combined flash read bandwidth.