First-generation ESP32 has an exceptionally weird low-power core. Retroactively, espressif called this "FSM ULP". For example, among other weirdness, this core has only one way to write memory that:
- writes only 32-bit words;
- only at 32-bit-aligned addresses;
- user program only controls lower 16 bits of the word;
- upper 16 bits are written with, basically, garbage (part of program counter).
Second-generation, ESP32-S2 is supposed to have a regular RISC-V low-power CPU core, in addition to the FSM.
- writes only 32-bit words;
- only at 32-bit-aligned addresses;
- user program only controls lower 16 bits of the word;
- upper 16 bits are written with, basically, garbage (part of program counter).
Second-generation, ESP32-S2 is supposed to have a regular RISC-V low-power CPU core, in addition to the FSM.