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baobrien
on Feb 18, 2018
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Ariane RISC-V CPU
Like rwmj says, ask somebody at SiFive -- but if I had to guess, I'd say it only breaks out some low speed IO/GPIO lines and a few chiplink lanes. That is to say if you want anything high speed, you're going to have to go through an FPGA board.
Consider applying for YC's Summer 2026 batch! Applications are open till May 4
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