I like the idea, but unfortunately PCIe isn't easy or cheap to implement on silicon. The problem is that you'd need the PHY, which is the high speed, analog interface, and that needs to be designed and tuned for the fab and process node you're targeting. In practice the only sane way to get PCIe on your chip is to buy a PCIe IP block from Faraday or Synopsys. The same goes for SATA. Ethernet and USB on the other hand is available in discrete PHY chips, so writing some open-source controller RTL for RGMII and ULPI is much more reasonable for an open-source chip. (Obviously, if someone would cough up the money for taping out a RISC-V SoC with PCIe PHYs onboard and make it in a large enough volume that the price gets down to reasonable levels, I'd be buying a bunch of'em.)