Agreed. It seams to me like the both CPU and FPGA would be both bound by the speed of their memories for the KV store. That's why I'm not sure why it would be beneficial to put it on a FPGA.
Skimming their summary, conclusion & comparison I can't really find a a good answer to it. Not saying it's a cool project but I don't see a practical case / nor pushing anything forward.
I imagine a pretty low-end server class x86 processor should be able to saturate most network links. There prob is a fair overhead going from network device, memory, OS, process and back out. But you could have your KV run in kernel space or as a real time process with dedicated core(s) / network device (memory mapped).
In an FPGA based design you can have many more memory channels and have them be dedicated for this purpose. Packet processing can also be done on the wire, giving you deterministic low latency access to memory storage.
Skimming their summary, conclusion & comparison I can't really find a a good answer to it. Not saying it's a cool project but I don't see a practical case / nor pushing anything forward.
I imagine a pretty low-end server class x86 processor should be able to saturate most network links. There prob is a fair overhead going from network device, memory, OS, process and back out. But you could have your KV run in kernel space or as a real time process with dedicated core(s) / network device (memory mapped).